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ASAHI KASEI
[AK4365]
AK4365
DAC with built-in PLL & HP-AMP
GENERAL DESCRIPTION The AK4365 is 20bit DAC with built-in PLL and Headphone Amplifier. The PLL input crystal frequency is matched to typical mobile phone clock frequencies. The AK4365 features an analog mixing circuit that allows easy interfacing in mobile phone and portable communication designs. The integrated headphone amplifier features "click-free" power-on/off, a mute control and delivers 10mW of power at 16. The AK4365 is housed in a 28pin QFN package, making it suitable for portable applications. FEATURE o Multi-bit DAC o Sampling Rate - 8kHz, 11.025kHz,16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz and 48kHz o On chip perfect filtering 8 times FIR interpolator - Passband: 20kHz - Passband Ripple: 0.02dB - Stopband Attenuation: 57dB o Digital De-emphasis Filter: 32kHz, 44.1kHz and 48kHz o PLL: - Input Frequency: 19.8MHz, 19.68MHz, 19.2MHz, 15.36MHz, 14.4MHz, 13MHz, 12MHz and 11.2896MHz - Input Level: CMOS or 0.4Vpp Analog Input o Audio I/F Format: MSB First, 2's Compliment - I2S, 20bit MSB justified, 20bit/16bit LSB justified - Master/Slave Mode o Digital ATT o Analog Mixing Circuit o Mono Lineout o P Interface: 3-wire o Low Frequency Boost Function o Headphone Amplifier - Output Power: 10mW x 2ch @16 (THD+N=0.3%) - S/N: 88dB - Click Noise Free at Power-ON/OFF and Mute o Power Supply: 3V10% o Power Supply Current: 11.5mA (@HP-AMP no-input) o Ta: -30 85C o Small Package: 28pin QFN
MS0110-E-01 -1-
2003/10
ASAHI KASEI
[AK4365]
PLLVCC
PLLGND
MCKO
MIN
LIN
AVDD
MCKI VCOC
PLL
MCLK
VREF
MINR MINL
VREF VCOM
VCOM
LIN
DVDD SDATA BICK LRCK Audio Interface ATT DAC
(Lch)
DACL
Head Phone Amp
LINM
HPL
DACM
ATT
DAC
(Mono)
Buffer amp
DACR
MOUT
RINM
SMODE
ATT
DAC
(Rch)
Head Phone Amp
HPR
RIN
RSTN CCLK CDTI CS DGND RIN AGND Serial I/F
HPVCC HPGND MUTET
Figure 1. AK4365 Block Diagram
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ASAHI KASEI
[AK4365]
n Ordering Guide
AK4365VN AKD4365 -30 +85C 28pin QFN (0.5mm pitch) Evaluation board for AK4365
n Pin Layout
PLLGND
MCKO
PLLVCC
MOUT
VCOC
28
27
26
25
24
23
HPL
CS CDTI CCLK LRCK BICK SDATA DVDD
1 2 3 4 5 6 7 10 12 13 14 8 9 11 Top View
22 21 20 19 18 17 16 15
HPR
HPGND HPVCC MUTET VCOM VREF AVDD AGND
SMODE
DGND
RSTN
MCKI
MIN
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RIN
LIN
2003/10
ASAHI KASEI
[AK4365]
PIN/FUNCTION
No. 1 2 3 4 Pin Name CS CDTI CCLK LRCK I/O I I I I/O Function Control Data Chip Select Pin Control Data Input Pin Control Clock Input Pin L/R Clock Pin This clock determines which audio channel is currently being input on SDATA pin. When SMODE pin = "L", a clock with fs rate is output. This pin is fixed to "L" at power-down. When SMODE pin = "H", a L/R clock is input. Serial Bit Clock Pin This clock is used to latch audio data. When SMODE pin = "L", a clock with 32fs or 64fs rate is output. This pin is fixed to "L" at power-down. When SMODE pin = "H", a bit clock is input. Audio Data Input Pin Digital Power Supply Pin Digital Ground Pin Master Clock Input Pin Reset Pin When at "L", the AK4365 is in power-down mode and is held in reset. The AK4365 should always be reset upon power-up. Master/Slave Mode Select Pin "L": Master Mode, "H": Slave Mode Mono Analog Input Pin Lch Analog Input Pin Rch Analog Input Pin Analog Ground Pin Analog Power Supply Pin Reference Voltage Output Pin, 2.0V (typ, respect to AGND) Normally connected to AGND pin with 0.1F ceramic capacitor in parallel with a 10F electrolytic capacitor. Common Voltage Output Pin, 1.0V (typ, respect to AGND) Normally connected to AGND pin with 0.1F ceramic capacitor in parallel with a 1F electrolytic capacitor. Mute Time Constant Control Pin Connected to AGND pin with a capacitor for mute time constant. Power Supply Pin for Headphone Amplifier Ground Pin for Headphone Amplifier Rch Headphone Amplifier Output Pin Lch Headphone Amplifier Output Pin Monaural Analog Output Pin Ground Pin for PLL. Connected to AGND. Output Pin for Loop Filter of PLL Circuit This pin should be connected to AGND with one resistor and one capacitor in series. Power Supply Pin for PLL. Normally connected to AVDD. Master Clock Output Pin
5 6 7 8 9 10 11 12 13 14 15 16 17
BICK SDATA DVDD DGND MCKI RSTN SMODE MIN LIN RIN AGND AVDD VREF
I/O I I I I I I I O
18 19 20 21 22 23 24 25 26 27 28
VCOM MUTET HPVCC HPGND HPR HPL MOUT PLLGND VCOC PLLVCC MCKO
O O O O O O O
Note: All digital input pins must not be left floating.
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ASAHI KASEI
[AK4365]
ABSOLUATE MAXIMUM RATING
(AGND, DGND, HPGND, PLLGND=0V; Note 1) Parameter Symbol min max AVDD Power Supplies Analog 4.6 -0.3 DVDD Digital 4.6 -0.3 PLLVCC PLL 4.6 -0.3 HPVCC HP-AMP 4.6 -0.3 |AGND - HPGND| (Note 2) GND1 0.3 |AGND - DGND| (Note 2) 0.3 GND2 |AGND - PLLGND| (Note 2) 0.3 GND3 Input Current (any pins except for supplies) IIN 10 Analog Input Voltage (LIN, RIN, MIN pins) VINA -0.3 AVDD+0.3 or 4.6 Digital Input Voltage VIND -0.3 DVDD+0.3 or 4.6 Ambient Temperature Ta -30 85 Storage Temperature Tstg -65 150 Note 1. All voltages with respect to ground. Note 2. AGND, DGND, HPGND and PLLGND must be connected to the same analog ground plane. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Units V V V V V V V mA V V C C
RECOMMEND OPERATING CONDITIONS
(AGND, DGND, HPGND, PLLGND=0V; Note 1) Parameter Symbol min typ max Units Power Supplies Analog (Note 3) AVDD 2.7 or (HPVCC - 0.4) 2.9 3.3 V Digital DVDD 2.7 2.9 3.3 V PLL PLLVCC 2.7 2.9 3.3 V HP-AMP HPVCC 2.7 2.9 3.3 V Note 1. All voltages with respect to ground. Note 3. Minimum value is higher value between 2.7V and (HPVCC - 0.4)V. Note 4. Figure 24 and Figure 25 shows the sequence in case that only AVDD is powered ON/OFF when DVDD is powered ON. * AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
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ASAHI KASEI
[AK4365]
ANALOG CHARACTERISTICS
(Ta=25C; AVDD=PLLVCC=DVDD=HPVCC=2.9V,AGND=PLLGND=DGND=HPGND=0V; fs=44.1kHz; EXT=1; BOOST OFF; Slave Mode; Signal Frequency =1kHz; Measurement band width=10Hz 20kHz; Load impedance is a serial connection with RL =16 and CL=220F. (Refer to Figure 26); unless otherwise specified) Parameter min typ max Units DAC Resolution 20 bit LINEIN: (LIN/RIN/MIN pins) Analog Input Characteristics Input Resistance 14 20 26 k Gain (Note 5) +5 +6 +7 dB Headphone-Amp: (HPL/HPR pins) (Note 6) Analog Output Characteristics THD+N (0dBFS Output) -50 -40 dB D-Range (-60dBFS Output, A-weighted) 82 88 dB S/N (A-weighted) 82 88 dB Interchannel Isolation 55 80 dB DC Accuracy Interchannel Gain Mismatch 0.3 0.5 dB Gain Drift 200 ppm/C Load Resistance (Note 7) 16 Load Capacitance 300 pF Output Voltage 1.00 1.12 1.24 Vpp Mono Output: (MOUT pin) (Note 8) Analog Output Characteristics: THD+N (0dBFS Output) -80 -65 dB S/N (A-weighted) 79 85 dB DC Accuracy Gain Drift 200 ppm/C Load Resistance (Note 7) 10 k Load Capacitance 25 pF Output Voltage 1.00 1.12 1.24 Vpp Power Supplies Power Supply Current Normal Operation (DAC=HPL=HPR=MOUT= "1") AVDD + PLLVCC + DVDD + HPVCC (Note 9) 11.5 18 mA Power-Down Mode (DAC=HPL=HPR=MOUT= "0") AVDD + PLLVCC + DVDD + HPVCC (Note 10) 1 100 A Power Supply Rejection (Note 11) 50 dB Note 5. Analog signal inputted from LIN/RIN/MIN pin is gained to +6dB internally. Note 6. DACL=DACR= "1", MINL=MINR=LIN=RIN= "0" Note 7. AC Load Note 8. DACM= "1", LINM=RINM= "0" Note 9. HP-Amp no output. MCKO = "0" Note 10. MINL=MINR=LIN=RIN= "0". In power-down mode, all digital input pins including clock pins (MCKI, BICK and LRCK) are held at DVDD or DGND. RSTN pin is held at DGND. In case of MINL, MINR, LIN, RIN, LINM or RINM = "1", the power supply current of AVDD pin is about 0.5mA (typ.). Note 11. PSR is applied to AVDD, PLLVCC, DVDD and HPVCC with 1kHz, 100mVpp.
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ASAHI KASEI
[AK4365]
FILTER CHARACTERISTICS
(Ta=25C; AVDD, DVDD, PLLVCC, HPVCC=2.7 3.3V; fs=44.1kHz; De-emphasis = "OFF") Parameter Symbol min typ max Units DAC Digital Filter: (Note 12) Passband -0.05dB (Note 13) PB 0 20.0 kHz -6.0dB 22.05 kHz Stopband (Note 13) SB 24.1 kHz Passband Ripple PR dB 0.02 Stopband Attenuation SA 57 dB Group Delay (Note 14) GD 19.1 1/fs Group Delay Distortion 0 GD s DAC Digital Filter + Analog Filter: (Note 12)(Note 15) FR dB 0.5 Frequency Response 0 20.0kHz Analog Filter: (Note 16) FR dB 1.0 Frequency Response 0 20.0kHz BOOST Filter: (Note 15) (Note 17) Frequency Response 20Hz FR -4.21 dB MIN 100Hz -7.03 dB 1kHz -10 dB 20Hz FR -4.05 dB MID 100Hz -6.04 dB 1kHz -9.9 dB 20Hz FR -4.34 dB MAX 100Hz -5.35 dB 1kHz -9.7 dB Note 12. BOOST OFF (BST1-0 = "00") Note 13. The passband and stopband frequencies scale with fs. For example, PB=0.4535*fs(@0.05dB), SB=0.546*fs(@-57dB). Note 14. This is the calculated delay time caused by digital filtering. This time is measured from the setting of the 20bit data of both channels to the input registers to the output of the analog signal. Note 15. DACL a HPL, DACR a HPR, DACM a MOUT Note 16. MIN a HPL/HPR, LIN a HPL/MOUT, RIN a HPR/MOUT Note 17. These frequency responses are characteristics with BOOST ON and -10dBFS digital data input.
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ASAHI KASEI
[AK4365]
Boost Frequency (fs=44.1kHz) 0 mid Level [dB] -5 max -10
min
-15 0.01
0.1 frequency[kHz]
1
10
Figure 2. Boost Frequency (fs=44.1kHz)
DC CHARACTERISTICS
(Ta=25C; AVDD, DVDD, PLLVCC = 2.7 3.3V) Parameter Symbol High-Level Input Voltage VIH Low-Level Input Voltage VIL Input Voltage at AC Coupling (Note 18) VAC VOH High-Level Output Voltage (Iout = -400A) VOL Low-Level Output Voltage (Iout = 400A) Input Leakage Current Iin Note 18. Only MCKI pin. (Figure 26) min 70%DVDD 0.4 DVDD-0.4 typ max 30%DVDD 0.4 10 Units V V Vpp V V A
-
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ASAHI KASEI
[AK4365]
SWITCHING CHARACTERISTICS
(Ta=25C; AVDD, DVDD, PLLVCC = 2.7 3.3V: CL = 20pF) Parameter Symbol Master Clock Timing Frequency (EXT= "0") fCLK (EXT= "1") fCLK Pulse Width Low (Note 19) tCLKL Pulse Width High (Note 19) tCLKH AC Pulse Width (Note 23) tACW LRCK Frequency fs Duty Cycle: Slave Mode Duty Master Mode Duty MCKO Output (PLL mode) Frequency fCLKO Duty Cycle (except fs=32kHz, PS1-0= "00") dMCK (fs=32kHz, PS1-0= "00") dMCK Serial Interface Timing (Note 20) min 11.2896 2.048 0.4/fCLK 0.4/fCLK 20 8 45 44.1 50 0.256 40 30 12.288 60 70 typ max 19.8 12.288 Units MHz MHz ns ns ns kHz % % MHz % %
48 55
Slave Mode (SMODE = "H"): BICK Period tBCK 312.5 ns BICK Pulse Width Low tBCKL 100 ns Pulse Width High tBCKH 100 ns tLRB 50 ns LRCK Edge to BICK "" (Note 21) tBLR 50 ns BICK "" to LRCK Edge (Note 21) tSDH 50 ns SDATA Hold Time tSDS 50 ns SDATA Setup Time Master Mode (SMODE = "L"): BICK Frequency (BF = "0") fBCK 64fs Hz (BF = "1") fBCK 32fs Hz BICK Duty dBCK 50 % tMBLR -50 50 ns BICK "" to LRCK tSDH 50 ns SDATA Hold Time tSDS 50 ns SDATA Setup Time Control Interface Timing CCLK Period tCCK 200 ns CCLK Pulse Width Low tCCKL 80 ns Pulse Width High tCCKH 80 ns CDTI Setup Time tCDS 40 ns CDTI Hold Time tCDH 40 ns CS "H" Time tCSW 150 ns CS "L" Time tCSW 150 ns CS "" to CCLK "" tCSS 150 ns tCSH 50 ns CCLK "" to CS "" Reset Timing RSTN Pulse Width (Note 22) tRST 300 ns Note 19. Except AC coupling. Note 20. Refer to "Serial Data Interface". Note 21. BICK rising edge must not occur at the same time as LRCK edge. Note 22. The AK4365 can be reset by bringing RSTN= "L" to "H" only upon power up. Note 23. Pulse width to ground level when MCKI is connected to a capacitor in series and a resistor is connected to ground. (Refer to Figure 3.)
MS0110-E-01 -9-
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ASAHI KASEI
[AK4365]
n Timing Diagram
1/fCLK
1000pF MCKI Input 100k AGND Measurement Point AGND
tACW
tACW
Figure 3. MCKI AC Coupling Timing 1/fCLK VIH VIL tCLKH tCLKL
MCKI
1/fs VIH VIL
LRCK
tBCK VIH VIL tBCKH tBCKL
BICK
MCKO tH tL dMCK=tH/(tH+tL) or tL/(tH+tL) Figure 4. Clock Timing
50% DVDD
MS0110-E-01 - 10 -
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ASAHI KASEI
[AK4365]
LRCK tBLR tLRB
VIH VIL
BICK tSDS tSDH
VIH VIL
SDATA
VIH VIL Figure 5. Serial Interface Timing (Slave Mode)
LRCK
50%DVDD
tMBLR
BICK tSDH
50%DVDD
tSDS
SDATA
VIH VIL Figure 6. Serial Interface Timing (Master mode) tRST
RSTN Figure 7. Power-down & Reset Timing
VIL
MS0110-E-01 - 11 -
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ASAHI KASEI
[AK4365]
CS tCSS CCLK tCDS CDTI D7 D6 tCDH D5 D4 tCCKL tCCKH
VIH VIL VIH VIL VIH VIL
Figure 8. WRITE Command Input Timing
tCSW CS tCSH CCLK VIH VIL VIH VIL VIH VIL
CDTI
A3
A2
A1
A0
Figure 9. WRITE Data Input Timing
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ASAHI KASEI
[AK4365]
OPERATION OVERVIEW n System Clock
1) PLL mode (EXT bit = "0") A fully integrated analog phase locked loop (PLL) generates a clock that is selected by PLL2-0 and FS2-0 bits (refer to Table 1 and Table 2). MCKO output frequency can be controlled by PS1-0 bits (addr=8FH, Table 3). MCKO output can be enabled by controlling MCKO bit. The lock time of PLL is 20ms from the changing of sampling frequency, and it is also 20ms after a stable MCKI clock is attained after power-up. To decrease output noise from DAC, serial input data is zeroed internally when PLL is not locked. When DAC is powered-up (DAC bit = "1") from power-down state (DAC bit = "0"), there is a 5ms delay before the internal circuit starts up. When changing the sampling frequency during normal operation (DAC bit = "1"), the change of sampling frequency should occur after the input is muted, or input to "0" data. LRCK and BICK are output from the AK4365 in master mode. When the clock input to MCKI pin stops during normal operation (DAC bit = "1"), the internal PLL oscillates (freewheels) at a few MHz, and LRCK and BICK outputs go to "L" (refer to Table 4). LRCK input should be synchronized with MCKI or MCKO at slave mode. LRCK and BICK should always be present whenever the AK4365 is in normal operation mode (DAC bit = "1"). If these clocks are not provided, the AK4365 may draw excess current and will not operate properly because it utilizes these clocks for internal dynamic refresh of registers. If the external clocks are not present, the AK4365 should be placed in the power-down mode (DAC bit = "0"). Mode 0 1 2 3 4 5 6 7 PLL2 0 0 0 0 1 1 1 1 PLL1 0 0 1 1 0 0 1 1 PLL0 0 1 0 1 0 1 0 1 MCKI 11.2896MHz 14.4MHz 12MHz 19.2MHz 15.36MHz 13MHz 19.68MHz 19.8MHz
Default
Table 1. MCKI Input Frequency (PLL mode) Mode 0 1 2 3 4 5 6 7 FS2 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 fs 48kHz 24kHz 32kHz 16kHz 44.1kHz 22.05kHz 11.025kHz 8kHz
Default
Table 2. Sampling Frequency (PLL mode)
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ASAHI KASEI
[AK4365]
PS1 0 0 1 1
PS0 0 1 0 1
MCKO 256fs 128fs 64fs 32fs
Default
Table 3. MCKO frequency (PLL mode, MCKO bit = "1") Master Mode (SMODE = "L") Power Down (DAC bit = "0") Don't care "L" "L" "L"
MCKI pin MCKO pin BICK pin LRCK pin
Power Up (DAC bit = "1") Refer to Table 1 MCKO bit = "0": "L" MCKO bit = "1": Output BF bit = "1": 64fs output BF bit = "0": 32fs output Output
PLL Unlock Refer to Table 1 MCKO bit = "0": "L" MCKO bit = "1": Unsettling "L" "L"
Table 4. Clock Operation at Master mode Slave Mode (SMODE = "H") Power Down (DAC bit = "0") Don't care "L" Fixed to "L" or "H" externally Fixed to "L" or "H" externally
MCKI pin MCKO pin BICK pin LRCK pin
Power Up (DAC bit = "1") Refer to Table 1 MCKO bit = "0": "L" MCKO bit = "1":Output Input Input
PLL Unlock Refer to Table 1 MCKO bit = "0": "L" MCKO bit = "1": Unsettling Input Input
Table 5. Clock Operation at Slave mode 2) EXT mode (EXT bit = "1") The AK4365 can be set to external clock mode (EXT mode) by setting EXT bit (control register: 8FH) to "1". In EXT mode, the master clock can be directly input to DAC via MCKI pin without PLL. In this case, the sampling frequency and MCKI frequency can be selected by FS2-0 bits (refer to Table 6). In EXT mode, PLL2-0 bits are ignored. Table 6 shows typical sampling frequencies. The sampling frequency can be adjusted from 8kHz to 48kHz by leaving FS2-0 bits fixed and altering the MCKI frequency. For example, when MCKI=256fs, the sampling frequency can be changed from 8kHz to 48kHz. MCKO output is enabled by controlling MCKO bit. MCKO output frequency can be controlled by PS1-0 bits. When DAC is powered-up (DAC bit = "1") from power-down state (DAC bit = "0"), there is a 5ms delay prior to internal circuit starting up. When changing the sampling frequency during normal operation (DAC bit = "1"), the change of sampling frequency should occur after the input is muted, or input to "0" data. LRCK and BICK are output from the AK4365 in master mode. The clock input to MCKI pin should always be present whenever the AK4365 is in normal operation (DAC bit = "1"). If these clocks are not provided, the AK4365 may draw excess current and will not operate properly because it utilizes these clocks for internal dynamic refresh of registers. If the external clocks are not present, the AK4365 should be placed in the power-down mode (DAC bit = "0"). The external clocks required to operate the AK4365 in slave mode are MCKI, LRCK and BICK. The master clock (MCKI) should be synchronized with sampling clock (LRCK). The phase between these clocks does not matter. All external clocks (MCKI, BICK and LRCK) should always be present whenever the AK4365 is in normal operation mode (DAC bit = "1"). If these clocks are not provided, the AK4365 may draw excess current and will not operate properly because it utilizes these clocks for internal dynamic refresh of registers. If the external clocks are not present, the AK4365 should be placed in the power-down mode (DAC bit = "0").
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ASAHI KASEI
[AK4365]
Mode 0 1 2 3 4 5 6 7
FS2 0 0 0 0 1 1 1 1
FS1 0 0 1 1 0 0 1 1
FS0 0 1 0 1 0 1 0 1
fs 48kHz 24kHz 32kHz 16kHz 44.1kHz 22.05kHz 11.025kHz 8kHz
MCKI 256fs 512fs 256fs 512fs 256fs 512fs 1024fs 1024fs
Default
Table 6. Relationship between Sampling Frequency and MCKI Frequency (EXT mode) PS1 0 0 1 1 PS0 0 1 0 1 MCKO 256fs 128fs 64fs 32fs
Default
Table 7. MCKO frequency (EXT mode, MCKO bit = "1) Master Mode (SMODE = "L") Power Up (DAC bit = "1") Power Down (DAC bit = "0") MCKI pin Refer to Table 6 Don't care MCKO pin MCKO bit = "0": "L" "L" MCKO bit = "1": Output BICK pin BF bit = "1": 64fs output "L" BF bit = "0": 32fs output LRCK pin Output "L" Table 8. Clock Operation at Master mode (EXT mode) Slave Mode (SMODE = "H") Power Up (DAC bit = "1") Power Down (DAC bit = "0") Refer to Table 6 Don't care MCKO bit = "0": "L" "L" MCKO bit = "1": Output Input Fixed to "L" or "H" externally Input Fixed to "L" or "H" externally Table 9. Clock Operation at Slave mode (EXT mode)
MCKI pin MCKO pin BICK pin LRCK pin
When low sampling rate, DR and S/N degrade because of the outband noise. DR and S/N are approved by using higher frequency for MCKI. Table 10 shows DR and S/N in the case DAC output to HP-amp. DR, S/N (A-weight) fs=8kHz fs=16kHz 256fs 63dB 81dB 512fs 81dB 88dB 1024fs 88dB N/A Table 10. Relationship between MCKI frequency and DR (and S/N) of HP-amp MCKI
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ASAHI KASEI
[AK4365]
n Serial Data Interface
The AK4365 interfaces with external system by using SDATA, BICK and LRCK pins. Four data formats are available and are selected by setting DIF0 and DIF1 bits. Mode 0 is compatible with existing 16bit DACs and digital filters. Mode 1 is a 20bit version of Mode 0. Mode 2 is similar to AKM ADCs and many DSP serial ports. Mode 3 is compatible with the I 2S serial data protocol. In Mode 2 and 3, 16bit data followed by four zeros also could be input, 18bit data followed by two zeros also could be input. In all modes, the serial data is MSB first and 2's complement format. When master mode and BICK=32fs(BF bit = "0"), the AK4365 cannot be set to Mode 1 or Mode 2. DIF1 bit 0 0 1 1 DIF0 bit 0 1 0 1 MODE 0: 16bit, LSB justified 1: 20bit, LSB justified 2: 20bit, MSB justified 3: I2S Compatible BICK 32fs 40fs 40fs 32fs or 40fs Figure Figure 10 Figure 10 Figure 11 Figure 12
Table 11. Audio Data Format
LRCK
Lch
Rch
BICK SDATA Mode:0 SDATA Mode:1
Don't care 15 0 Don't care 15 0
Don't care
19
16
15
0
Don't care
19
16
15
0
15:MSB, 0:LSB (@16bit Data) 19:MSB, 0:LSB (@20bit Data) Mode 1: BICK needs 40fs or more than 40fs
Figure 10. Mode 0,1 Timing
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ASAHI KASEI
[AK4365]
LRCK
Lch
Rch
BICK SDATA 16bit SDATA 18bit SDATA 20bit
15 14 0 Don't care 15 14 Don't care
0
15
14
17
16
2
1
0
Don't care
17
16
2
1
0
Don't care
17
16
19
18
4
3
2
1
0
Don't care
19
18
4
3
2
1
0
Don't care
19
18
* BICK needs more than 40fs.
Figure 11. Mode 2 Timing
LRCK BICK SDATA 16bit SDATA 18bit SDATA 20bit
15 14
Lch
Rch
0
Don't care
15
14
0
Don't care
15
17
16
2
1
0
Don't care
17
16
2
1
0
Don't care
17
19
18
4
3
2
1
0
Don't care
19
18
4
3
2
1
0
Don't care
19
* BICK needs more than 40fs.
BICK (32fs) SDATA 16bit
0 15 14 6 5 4 3 2 1 0 15 14 6 5 4 3 2 1 0 15
Figure 12. Mode 3 Timing
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ASAHI KASEI
[AK4365]
n Serial Control Interface
Internal registers may be written to via the 3-wire P interface pins (CS, CCLK and CDTI). The data on this interface consists of Control data (MSB first, 8bits) and Register address (MSB first, 8bits). Address and data is clocked in on the rising edge of CCLK and data is clocked out on the falling edge. For WRITE operations, data is latched after a low-to-high transition of CS. The clock speed of CCLK is 5MHz (max). The value of internal registers is initialized at RSTN = "L". CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CCLK
CDTI
D7 D6 D5 D4 D3 D2 D1 D0 A7
A6
A5
A4 A3
A2
A1
A0
D7-D0: Control Data A7-A0: Register Address Figure 13. Control Interface
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ASAHI KASEI
[AK4365]
n Register Map
Addr 80H 81H 85H 88H 89H 8BH 8DH 8FH Register Name PLL Mode & Timer Mode Control Power Management Output Select 1 HP-Amp Rch ATT HP-Amp Lch ATT MOUT ATT Mode Control 2 D7 TM1 DIF1 MINR 0 ATTR7 ATTL7
ATTM7
D6 TM0 DIF0 MINL RINM ATTR6 ATTL6
ATTM6
D5 PLL2 MCKO BF LINM ATTR5 ATTL5
ATTM5
D4 PLL1 DEM MONO RIN ATTR4 ATTL4
ATTM4
D3 PLL0
LRMUTE
D2 FS2
MMUTE
MOUT LIN ATTR3 ATTL3
ATTM3
HPR DACM ATTR2 ATTL2
ATTM2
D1 FS1 BST1 HPL DACR ATTR1 ATTL1
ATTM1
D0 FS0 BST0 DAC DACL ATTR0 ATTL0
ATTM0
0
0
PS0
PS1
CKP
LRP
0
EXT
n Register Definitions
All registers inhibit writing at RSTN pin = "L". Addr 80H Register Name PLL Mode & Timer Default D7 TM1 0 D6 TM0 0 D5 PLL2 0 D4 PLL1 0 D3 PLL0 0 D2 FS2 1 D1 FS1 0 D0 FS0 0
FS2-0: Select Sampling Frequency PLL mode: Table 2 EXT mode: Table 6 PLL2-0: Select MCKI Frequency PLL mode: Table 1 EXT mode: Disable TM1-0: Soft Mute Time Setting. LRMUTE and MMUTE settings are linked together. TM1 TM0 Cycle Default 0 0 1024/fs 0 1 512/fs 1 0 256/fs 1 1 128/fs Table 12. Soft Mute Time Setting
MS0110-E-01 - 19 -
2003/10
ASAHI KASEI
[AK4365]
Addr 81H
Register Name Mode Control Default
D7 DIF1 0
D6 DIF0 0
D5 MCKO 0
D4 DEM 0
D3
LRMUTE
D2
MMUTE
0
0
D1 BST1 0
D0 BST0 0
BST1-0: Select Low Frequency Boost Function BST1 BST0 Mode 0 0 OFF Default 0 1 MIN 1 0 MID 1 1 MAX Table 13. Select Low Frequency Boost MMUTE: The output data from DACM is soft-muted. 0: Disable (Default) 1: Enable LRMUTE: The output data from DACL and DACR are soft-muted. 0: Disable (Default) 1: Enable DEM: De-emphasis Filter Frequency Select Sampling frequency of De-emphasis is selected by FS2-0 bits. Sampling frequency is enabled at 32kHz, 44.kHz and 48kHz only. DEM 0 FS2 0 0 0 0 1 1 1 1 FS1 FS0 Sampling Frequency 0 0 48kHz 0 1 24kHz 1 0 32kHz 1 1 16kHz 0 0 44.1kHz 0 1 22.05kHz 1 0 11.025kHz 1 1 8kHz Table 14. De-emphasis Filter Frequency Select De-emphasis OFF ON: 48kHz OFF ON: 32kHz OFF ON: 44.1kHz OFF OFF OFF
Default
1
MCKO: Control of MCKO signal 0: Disable (Default) 1: Enable DIF1-0: Audio Data Interface Format DIF1 0 0 1 1 DIF0 0 1 0 1 MODE BICK 0: 16bit, LSB justified 32fs 1: 20bit, LSB justified 40fs 2: 20bit, MSB justified 40fs 3: I2S Compatible 32fs or 40fs Table 15. Audio Data Interface Format Figure Figure 10 Figure 10 Figure 11 Figure 12
Default
MS0110-E-01 - 20 -
2003/10
ASAHI KASEI
[AK4365]
Addr 85H
Register Name Power Management Default
D7 MINR 0
D6 MINL 0
D5 BF 0
D4 MONO 0
D3 MOUT 0
D2 HPR 0
D1 HPL 0
D0 DAC 0
DAC: Power management for DACL, DACR, DACM and PLL. When this bit changes from "0" to "1", DAC is powered-up to the current register values (ATT value, sampling rate, etc). 0: Power OFF (Default) 1: Power ON HPL: Power management for Lch headphone amplifier. 0: Power OFF (Default). Output voltage becomes HPGND (0V). 1: Power ON HPR: Power management for Rch headphone amplifier 0: Power OFF (Default). Output voltage becomes HPGND (0V). 1: Power ON MOUT: Power management for monaural lineout 0: Power OFF (Default). Output voltage becomes Hi-z. 1: Power ON MONO: Control of the signal output from DACL and DACR 0: Normal Output (Default) 1: (L+R)/2 In case of DAC bit = "0", MONO bit is not ignored. When changing between Mono and Stereo modes, the headphone amplifiers should be powered-down. (HPL=HPR= "0"). When HPL/HPR bits are OFF ("0"), DAC and MOUT bits should also be OFF("0"). If HPL/HPR bits are changed to ON ("1") when DAC and MOUT are powered-up, the HP-AMP will remain off. HPL bit 0 0 0 0 1 1 1 1 HPR bit MONO bit HPL pin 0 0 HPGND 0 1 HPGND 1 0 HPGND 1 1 HPGND 0 0 Normal output 0 1 (L+R)/2 1 0 Normal output 1 1 (L+R)/2 Table 16. HPL/HPR pin Output Signal HPR pin HPGND HPGND Normal output (L+R)/2 HPGND HPGND Normal output (L+R)/2
Default
BF: BICK Period setting at Master Mode. In slave mode, this bit is ignored. 0: 32fs (Default) 1: 64fs MINL: The input signal from MIN pin is added to Lch of headphone amplifier. 0: OFF (Default) 1: ON MINR: The input signal from MIN pin is added to Rch of headphone amplifier. 0: OFF (Default) 1: ON * When the paths of MINL and MINR are changed, outputs of HP-Amp and MOUT should be muted.
MS0110-E-01 - 21 -
2003/10
ASAHI KASEI
[AK4365]
Addr 88H
Register Name Output Select 1 Default
D7 0 0
D6 RINM 0
D5 LINM 0
D4 RIN 0
D3 LIN 0
D2 DACM 0
D1 DACR 0
D0 DACL 0
DACL: Select an output path of DACL 0: OFF (Default) 1: ON DACR: Select an output path of DACR 0: OFF (Default) 1: ON DACM: Select an output path of DACM 0: OFF (Default) 1: ON LIN: The input signal from LIN pin is added to Lch of headphone amplifier. 0: OFF (Default) 1: ON RIN: The input signal from RIN pin is added to Rch of headphone amplifier. 0: OFF (Default) 1: ON LINM: The input signal from LIN pin is added to MOUT amplifier. 0: OFF (Default) 1: ON RINM: The input signal from RIN pin is added to MOUT amplifier. 0: OFF (Default) 1: ON * When these paths (DACL, DACR, DACM, LIN, RIN, LINM and RINM) are changed, outputs of HP-Amp and MOUT should be muted.
MS0110-E-01 - 22 -
2003/10
ASAHI KASEI
[AK4365]
Addr 89H 8BH 8DH
Register Name HP-Amp Rch ATT HP-Amp Lch ATT MOUT ATT Default
D7 ATTR7 ATTL7
ATTM7
D6 ATTR6 ATTL6
ATTM6
D5 ATTR5 ATTL5
ATTM5
D4 ATTR4 ATTL4
ATTM4
D3 ATTR3 ATTL3
ATTM3
D2 ATTR2 ATTL2
ATTM2
D1 ATTR1 ATTL1
ATTM1
D0 ATTR0 ATTL0
ATTM0
0
0
0
0
0
0
0
0
ATTR7-0: Setting of the attenuation value of output signal from DACR ATTL7-0: Setting of the attenuation value of output signal from DACL ATTM7-0: Setting of the attenuation value of output signal from DACM. The internal calculation is attenuated by 10bit linear value, but the available ATT value is 8bit. Table 17 shows typical ATT values. The transition between ATT values uses the same mechanism as the soft mute operation. For example, if the current value is ATT1 and a new value is set as ATT2, ATT1 transitions to ATT2. The time that it takes for this transition to occur is set via the TM1-0 bits. If the new value (ATT3) is set before ATT1 reaches ATT2, the ATT value will transition directly to the ATT3 setting. Equation of attenuation level: FFH: 0dB FEH 20H: ATT = 20 x log10 ((Register Value x 4) - 60H) / 1023) [dB] 1FH 01H: ATT = 20 x log10 ((Register Value) / 1023) [dB] 00H: MUTE DATA FFH FCH E3H CDH B9H A8H 98H 8AH 7EH 73H 69H 60H 58H 51H 4BH 45H 41H 3CH 38H 35H 31H 2FH 2CH 2AH 28H 26H ATT [dB] DATA ATT [dB] 0.0 25H -25.877 -0.998 23H -27.328 -2.006 22H -28.156 -3.003 21H -29.017 -4.020 20H -30.095 -4.989 1DH -30.950 -6.012 1AH -31.898 -7.018 16H -32.963 -7.984 14H -34.177 -8.975 12H -35.092 -9.987 10H -36.115 -11.010 0EH -37.275 -12.033 0DH -37.919 -13.039 0BH -39.370 -14.005 0AH -40.198 -15.092 09H -41.113 -15.901 08H -42.136 -17.030 07H -43.296 -18.053 06H -44.634 -18.908 05H -46.218 -20.198 04H -48.156 -20.922 03H -50.655 -22.136 02H -54.177 -23.051 01H -60.198 -24.074 00H MUTE -25.234 Table 17. Typical ATT values
MS0110-E-01 - 23 -
2003/10
ASAHI KASEI
[AK4365]
Addr 8FH
Register Name Mode Control 2 Default
D7 0 0
D6 0 0
D5 0 PS0
D4 0 PS1
D3 0 CKP
D2 0 LRP
D1 0 0
D0 EXT 0
EXT: Master Clock Mode Select 0: PLL mode 1: EXT mode (External clock mode) LRP: LRCK Polarity (enable at slave mode) 0: Normal 1: Invert CKP: BICK Polarity (enable at slave mode) 0: Normal 1: Invert PS1-0: MCKO Frequency PLL mode: Table 3 EXT mode: Table 7
MS0110-E-01 - 24 -
2003/10
ASAHI KASEI
[AK4365]
n Soft Mute
Soft mute operation is performed in the digital domain. When LRMUTE or MMUTE bit go to "1", the output signal is attenuated by - ("0") via the cycle set by TM1-0 bit (Table 12). When LRMUTE or MMUTE bit is returned to "0", the mute is cancelled and the output attenuation gradually changes to 0dB via the cycle set of TM1-0 bits. LRMUTE and MMUTE bits operate independently. If the soft mute is cancelled within the cycle set by TM1-0 bits after starting the operation, the attenuation is discontinued and returned to 0dB. The soft mute is effective for changing the signal source without stopping the signal transmission.
LRMUTE bit or MMUTE bit 0dB Attenuation
TM1-0 bit (1)
TM1-0 bit (3)
-
GD (2) Analog Output GD
Figure 14. Soft Mute Function NOTE: (1) The output signal is attenuated until - ("0") by the cycle set by TM1-0 bit (2) Analog output corresponding to digital input have the group delay (GD). (3) If the soft mute is cancelled within the cycle of setting TM1-0 bit, the attenuation is discontinued and returned to 0dB(the setting value).
n De-emphasis Filter
The AK4365 includes a digital de-emphasis filter (tc = 50/15s) by IIR filter corresponding to three sampling frequencies (32kHz, 44.1kHz and 48kHz). The de-emphasis filter is enabled by setting FS2-0 and DEM bits.
MS0110-E-01 - 25 -
2003/10
ASAHI KASEI
[AK4365]
n Low Frequency Boost Function
By controlling BST1-0 bits, the low frequency boost signal can be output from DACL, DACR and DACM. The setting value is common in DACL, DACR and DACM. Table 18 shows the relationship of external resistor, capacitor, fc(cut-off frequency) and output power, where load resistance of headphone is 16.
AK4365
HPL/R
C
R
16
Headphone
Figure 15. Headphone external circuit example
Fc Po Figure C[F] 45Hz Figure 16 220F 9.8mW 0 100Hz Figure 17 100F 70Hz Figure 18 100F 4.8mW 6.8 149Hz Figure 19 47F 50Hz Figure 20 100F 2.45mW 16 106Hz Figure 21 47F Table 18. Relationship of external circuit, output power and frequency response R[]
MS0110-E-01 - 26 -
2003/10
ASAHI KASEI
[AK4365]
10
5
0 LEVEL[dB]
-5
OFF MIN MID MAX
-10
-15
-20 0.01
0.10 Frequency [kHz]
1.00
10.00
Figure 16. C=220F, R = 0, fs=44.1kHz
5
0
LEVEL[dB]
-5
OFF MIN MID MAX
-10
-15
-20 0.01
0.10 Frequency [kHz]
1.00
10.00
Figure 17. C=100F, R = 0, fs=44.1kHz
MS0110-E-01 - 27 -
2003/10
ASAHI KASEI
[AK4365]
5
0
LEVEL[dB]
-5
OFF MIN MID MAX
-10
-15
-20 0.01
0.10 Frequency [kHz]
1.00
10.00
Figure 18. C=100F, R = 6.8, fs=44.1kHz
5
0
LEVEL[dB]
-5
OFF MIN MID MAX
-10
-15
-20 0.01
0.10 Frequency[kHz]
1.00
10.00
Figure 19. C=47F, R = 6.8, fs=44.1kHz
MS0110-E-01 - 28 -
2003/10
ASAHI KASEI
[AK4365]
5
0
LEVEL[dB]
-5
OFF MIN MID MAX
-10
-15
-20 0.01
0.10 Frequency[kHz]
1.00
10.00
Figure 20. C=100F, R = 16, fs=44.1kHz
5
0
LEVEL[dB]
-5
OFF MIN MID MAX
-10
-15
-20 0.01
0.10 Frequency[kHz]
1.00
10.00
Figure 21. C=47F, R = 16, fs=44.1kHz
MS0110-E-01 - 29 -
2003/10
ASAHI KASEI
[AK4365]
n Polarity and gain of Line Input/Output
The input signal from LIN, RIN and MIN pins are gained to +6dB by headphone amplifier. The input signal from LIN, RIN and MIN pins are inverted by headphone amplifier. The output signal from DAC is a non-inverted signal.
typ.20k
LIN/RIN pin
typ.20k
MIN pin
typ.40k
DACL/DACR
+ SMF
typ.40k
+ HP-Amp
HPL/HPR pin
Figure 22. Internal equivalent circuit between DACL/DACR and HPL/HPR
typ.20k
LIN pin
typ.20k
RIN pin
typ.40k
DACM
+ SMF
typ.40k
+
MOUT pin
Figure 23. Internal equivalent circuit between DACM and MOUT
n System Reset
The AK4365 should be reset once by bringing RSTN "L" upon power-up. After exiting reset, DAC, HPL, HPR and MOUT switch to the power-down state. The contents of the control register are maintained until the reset is done.
MS0110-E-01 - 30 -
2003/10
ASAHI KASEI
[AK4365]
n Power ON/OFF Sequence
1) In case of DAC output (Full-scale output) to HPL, HPR and MOUT pins (LIN, RIN and MIN: No input)
DVDD AVDD, PLLVCC, HPVCC RSTN pin DAC,HPL HPR,MOUT bit Clock IN (7) (5)
ATT7-0 bit HPL,HPR pin MOUT pin ATT7-0 bit HPL, HPR pin MOUT pin
00H (1) (4) (2)
FFH (2) (6) (3) (4) (2) (6)
00H
00H (1) (2)
FFH (2) (6) (3) (2) (6)
00H
FFH
(4)
(4)
Figure 24. Power ON/OFF Sequence (1) (1) Rise time of HP-Amp can be set by a capacitor connected to the MUTET pin. Rise time to 80% is 150ms(min), 300ms(typ) and 600ms(max) when the capacitor is 1F, and 70ms(min), 140ms(typ) and 290ms(max) when 0.47F. In case of 0.47F, pop noise may be bigger. (2) ATT7-0 bits are set to 00H on reset. When TM1-0 bits are "00", the attenuated signal is released by the cycle set by TM1-0 bits after ATT7-0 bits are set to FFH. (Same as soft mute) (3) When HPL and HPR go to HPGND, the power supplies to DAC and HP-Amp are powered-down. (4) When DAC and MOUT bits change to "1" or "0", click noise occurs from MOUT pin. When MOUT bit is "0", output of MOUT becomes Hi-Z. (5) After DAC, HPL, HPR and MOUT are powered-down once, it is necessary to wait this amount of time before they are powered-up again. (Time required prior to writing to DAC, HPL, HPR and MOUT bits.) If HPL and HPR bits are changed to "1" within this time, HP-Amp may not be powered-up. The time in which HP-Amp is not powered-up (this partial time is included in the time above) depends on a capacitor connected to the VCOM pin (C2), 0.8k x C2 (max). (6) Fall time of HP-Amp can be set by a capacitor connected to the MUTET pin. Fall time to 0V is 200ms(min), 400ms(typ) and 860ms(max) when the capacitor is 1F, and 90ms(min), 190ms(typ) and 410ms(max) when 0.47F. In case of 0.47F, pop noise may be bigger. (7) If only AVDD, PLLVCC and HPVCC are powered ON/OFF when DVDD is powered ON, the RSTN pin should be changed from "L" to "H" after AVDD, PLLVCC and HPVCC are powered ON. The time required prior to writing to DAC, HPL, HPR and MOUT bits(5) = Time(1) + Soft Mute Time(2) For example, MUTET pin = 1F, VCOM pin = 1F, fs = 44.1kHz, Soft mute time setting = 1024/fs (TM1-0 = "00") Time (1): max. 860ms Time (2): max. 23.2ms = 1024/fs + 1/fs @ fs=44.1kHz Time (5): 883.2ms = 860ms + 23.2ms For the example above, wait about 883.2ms before writing to DAC, HPL, HPR or MOUT bit. MS0110-E-01 - 31 2003/10
ASAHI KASEI
[AK4365]
* If it is necessary to shorten the MUTE sequence time, an external mute circuit should be implemented. An example of an external mute circuit is shown in the AK4365 evaluation board manual. The external mute circuit should be released after the HP-Amp is powered up. If the external mute is released on the way of HP-Amp power-up, large pop noise will occur. * Power supply AVDD is powered-up at the same time or earlier than power supply HPVCC. Power supply AVDD is powered-down at the same time or later than power supply HPVCC.
MS0110-E-01 - 32 -
2003/10
ASAHI KASEI
[AK4365]
2) In case of output from LIN, RIN and MIN pins (Full-scale output) to HPL, HPR and MOUT pins (DAC Power OFF)
DVDD AVDD, PLLVCC, HPVCC RSTN pin HPL,HPR MOUT bit HPL,HPR pin MOUT pin (3) (3) (4) (1)
(6)
(5) (2)
(5)
Figure 25. Power ON/OFF Sequence (2) (1) Rise time of HP-Amp can be set by a capacitor connected to the MUTET pin. Rise time to 80% is 150ms(min), 300ms(typ) and 600ms(max) when the capacitor is 1F, and 70ms(min), 140ms(typ) and 290ms(max) when 0.47F. In case of 0.47F, pop noise may be bigger. To rise common voltage, lower side of output signal is clipped. (2) When HPL and HPR go to HPGND, the power supply of HP-Amp is powered-down. (3) MOUT bit changes to "1" or "0", click noise occurs from MOUT pin. When MOUT bit is "0", output of MOUT becomes Hi-Z. (4) After DAC, HPL, HPR and MOUT are powered-down once, it is necessary to wait this amount of time before they are powered-up once again. (Time required prior to writing to DAC, HPL, HPR and MOUT bits.) If HPL and HPR bits are changed to "1" within this time, HP-Amp may not be powered-up. The time in which HP-Amp is not powered-up (this partial time is included in the time above) depends on a capacitor connected to the VCOM pin (C2), 0.8k x C2 (max). (5) Fall time of HP-Amp can be set by a capacitor connected to the MUTET pin. Fall time to 0V is 200ms(min), 400ms(typ) and 860ms(max) when the capacitor is 1F, and 90ms(min), 190ms(typ) and 410ms(max) when 0.47F. In case of 0.47F, pop noise may be bigger. To fall common voltage, lower side of output signal is clipped. (6) If only AVDD, PLLVCC and HPVCC are powered ON/OFF when DVDD is powered ON, the RSTN pin should be changed from "L" to "H" after AVDD, PLLVCC and HPVCC are powered ON. The time required prior to writing to DAC, HPL, HPR and MOUT bits (4) = Time (1) For example, MUTET pin = 1F, VCOM pin = 10F Time (1): max. 860ms Time (4) = Time (1) = 860ms For the example above, wait about 860ms writing to DAC, HPL, HPR or MOUT bit. * If it is necessary to shorten the MUTE sequence time, an external mute circuit should be implemented. An example of an external mute circuit is shown in the AK4365 evaluation board manual. The external mute circuit should be released after the HP-Amp is powered up. If the external mute is released on the way of HP-Amp power-up, large pop noise will occur. * Power supply of AVDD is powered-up at the same time or earlier than power supply of HPVCC. Power supply of AVDD is powered-down at the same time or later than power supply of HPVCC.
MS0110-E-01 - 33 -
2003/10
ASAHI KASEI
[AK4365]
SYSTEM DESIGN
Figure 26 shows the system connection diagram. An evaluation board [AKD4365] is available which demonstrates the optimum layout, power supply arrangements and measurement results. Capacitance values of VCOC pin PLL Frequency: 19.8MHz, 19.68MHz, 19.2MHz, 15.36MHz, 14.4MHz, 12MHz, 11.2896MHz a C = 4.7nF PLL Frequency: 13MHz aC = 470nF
10 + 0.1 C 10k 256fs 220 + + VCOC 26 PLLGND 25 MOUT 24 HPL 23 HPR 22 220 16 16
MCKO 28
Mode Setting 1 CS 2 CDTI 3 CCLK Audio Controller 4 LRCK 5 BICK
PLLVCC 27
HPGND 21 HPVCC 20 MUTET 19 0.1 1 10 + + 10 + 0.1 + 0.1 10 1
Headphone Analog Supply 2.73.3V
Top View
VCOM 18 0.1 VREF 17 AVDD 16
6 SDATA 11 SMODE 7 DVDD 8 DGND 10 RSTN 9 MCKI
Analog Supply 2.73.3V
AGND 15 12 MIN 14 RIN 13 LIN
0.1 10 +
1000p 10
Figure 26. Typical Connection Diagram (In case of AC coupling to MCKI)
MS0110-E-01 - 34 -
2003/10
ASAHI KASEI
[AK4365]
Note: The headphone amplifier output for the AK4365 may oscillate. This oscillation is caused by the load of a headphone cable. The following external circuit 1) or 2) should be used to avoid this oscillation. 1) Resistor (6.8) in series. In this case, the voltage at the headphone will be attenuated by resistor divider.
AK4365
HPL/R 16 220u 6.8
Headphone
Figure 27. Headphone amp external circuit example 1 2) Capacitor (0.1F20%) and resistor (1020%) in series to ground.
AK4365
HPL/R 0.1u 16 220u
10
Headphone
Figure 28. Headphone amp external circuit example 2
MS0110-E-01 - 35 -
2003/10
ASAHI KASEI
[AK4365]
1. Grounding and Power Supply Coupling
The AK4365 requires careful attention to power supply and grounding arrangements. AVDD is usually supplied from the analog power supply in the system and DVDD is supplied from AVDD via a 10 resistor. Alternatively if AVDD and DVDD are supplied separately, the power up sequence is not critical. When AVDD and HPVCC are supplied separately, AVDD is powered-up at the same time or earlier than HPVCC. When the AK4365 is powered-down, HPVCC is powered-down at the same time or later than AVDD. The power up sequence of PLLVCC is not critical. AGND, DGND, PLLGND and HPGND must be connected to the analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as close to the AK4365 as possible, with the small value ceramic capacitors being the nearest.
2. Internal Voltage Reference
Internal voltage reference is output on the VREF pin (typ. 2.0V). An electrolytic capacitor 10F in parallel with a 0.1F ceramic capacitor is attached between VREF and AGND to eliminate the effects of high frequency noise. VCOM is 1.0V(typ) and is a signal ground of this chip. A 1F electrolytic capacitor in parallel with a 0.1F ceramic capacitor should be connected between VCOM and AGND to eliminate the effects of high frequency noise. A ceramic capacitor should be connected to VCOM pin and located as close as possible to the AK4365. No load current may be drawn from VREF and VCOM pins. All signals, especially clocks, should be kept away from the VCOM and VREF pins in order to avoid unwanted coupling into the AK4365.
3. Analog Outputs
The analog outputs are single-ended outputs and 1.12Vpp(typ) centered around the VCOM voltage. The input data format is 2's compliment. The output voltage is a positive full scale for 7FFFF(@20bit) and negative full scale for 80000H(@20bit). The ideal output is VCOM voltage for 00000H(@20bit). If the noise generated by the delta-sigma modulator beyond the audio band causes problems, attenuation by an external filter is required. DC offsets on the analog outputs is eliminated by AC coupling since analog outputs have DC offsets of VCOM + a few mV.
MS0110-E-01 - 36 -
2003/10
ASAHI KASEI
[AK4365]
PACKAGE
28pin QFN (Unit: mm)
-C 0. 6
5.2 0.20 5.0 0.10 28 22 1 5.2 0.20 5.0 0.10 21 0.60 0.10
0. 2
+ 0 - 0 .10 .2 0
4
0.
22 21 45
28
25
0.
10
1 45
7 8 0.22 0.05 14 0.50
15
15 14 8
7
0.05 M
- 0.28
0.21 0.05
0.05
Note: The black parts of back package should be open.
n Package & Lead frame material
Package molding compound: Epoxy Lead frame material: Cu Lead frame surface treatment: Solder (Pb free) plate
MS0110-E-01 - 37 -
0.02 + 0.03
- 0.02
0.80 + 0.20
0.78 + 0.17
- 0.00
2003/10
ASAHI KASEI
[AK4365]
MARKING
4365
XXXX
1
XXXX : Date code identifier (4 digits)
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: a. A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
MS0110-E-01 - 38 -
2003/10

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